Random access memory (RAM) provides fast, cost-effective, volatile storage for computing devices. The Joint Electron Device Engineering Council (JEDEC) provides memory standards for storage devices. DDR4 SDRAM (double data rate fourth generation synchronous dynamic random-access memory) provides higher module density, lower voltage specifications and higher data rate transfer speeds. DDR4 LRDIMM (load reduced dual in-line memory module) technology uses a distributed buffer approach to implement memory bandwidth efficiencies when scaling to higher capacities and data rate transfer speeds.
Increasing data rate transfer speeds introduces new engineering challenges. To meet the JEDEC standards for data transfer, one of the challenges is to overcome loss in signal strength, and increased cross talk and reflections introduced by various components of the transmission channel (i.e., noise). Continuous time linear equalization (CTLE) is a technique used to boost high frequency signals in a specific range of interest. In traditional implementations, a differential input circuit with resistive and capacitive (RC) degeneration is used. In DDR4 applications, the amount of boosting a circuit gets is limited due to the amount of crosstalk. For most circuit designs, area is an important parameter. The amount of area used for a design impacts competitiveness parameters (i.e., cost effectiveness, power consumption, etc.). Conventional implementations of CTLE circuitry use more area and do not fit within aggressive target area parameters.
It would be desirable to implement a receiver CTLE circuit that minimizes cross talk and/or is implemented using a minimal amount of chip area.